Field of the Disclosure
The present disclosure generally relates to designing of an integrated circuit (IC), and specifically to using an overlay schematic over a base circuit schematic to generate a modified circuit design.
Description of the Related Arts
The design and verification of electronic circuits in an integrated circuit (IC) involves experimentation and debugging, typically accomplished with a schematic testbench and/or modifying of design schematics. In typical design and verification methodologies, the testbench is created as a new schematic containing an instance of the design under test along with relevant test sources, stimulus and loads. The design under test is typically treated as a black box accessed only through input/output ports while the internal nodes and instances are usually not modified if avoidable.
Modifications within the black box are error prone because it is difficult to differentiate between permanent design modifications and temporary test modifications. An alternative to modifying the design is to copy the schematics to a new library and make temporary changes outside of the base design schematics. Such alternative approach has the benefit of keeping test changes external to the base design data but suffers from synchronization issues. That is, if the base design data changes, the copied data must be updated as well with incremental changes. Further, in the absence of tools to analyze and propagate the incremental changes, the process is manual, tedious and error prone.
The testbench schematic also causes problems for post layout analysis because the testbench is not part of the layout hierarchy. Since the testbench does not have a physical layout representation, analysis tools maintain a correspondence between schematic and layout paths.